Andrew Dearborn

Promoted to Company Technical Staff (Executive Technical Leadership Track)

Role Overview:
Function as a strategic, cross-functional "Department of One" leading the absolute convergence of IT Infrastructure, CAD, DevOps, PDK, and EDA tracks. Transformed a legacy environment into a highly available, automated, and secure Heterogeneous HPC Semiconductor Design Environment. Transitioned from an initial onboarding role as Principal ASIC Engineer into TEL’s Technical Staff—a governing technical leadership body rather than a passive title, operating at a level equivalent to a Principal Engineer / Director scope. Handled full-spectrum technical execution while simultaneously owning vendor relations and high-stakes contract EDA negotiations.

TECHNICAL ARCHITECTURE & LEADERSHIP ACHIEVEMENTS

IT Infrastructure & HPC Fabric

• HPC & Load Balancing: Consolidated distributed bare-metal compute servers, high-speed nodes (25Gbps), and engineering workstations into a unified Slurm Workload Manager cluster to maximize multi-node utilization and job scheduling.
• Hyperconverged Foundation: Formed a highly resilient compute foundation by deploying Cisco HyperFlex HCI, enabling absolute service isolation, high availability, and 100% automated maintenance.
• Storage & Encryption Architecture: Engineered a high-performance, BTRFS/ZFS-based file server featuring native disk compression to maximize NVMe utilization, paired with disk encryption to secure block-level snapshots and guarantee rapid data recoverability.
• Unified Environment Mapping: Architected a dynamic, centralized NFS mapping schema that standardizes directory structures across all workstations and servers, allowing users to seamlessly transition between physical hosts and virtual endpoints while optimizing cluster load balancing.
• Datacenter Migration: Successfully orchestrated the end-to-end relocation of core engineering infrastructure between data centers with less than 4 hours of total downtime.
• Virtualization & Remote Access: Transitioned remote engineering teams off physical hardware and onto dedicated Desktop VMs hosted on HyperFlex, driving substantial data bandwidth improvements and block-level backup reliability.

CAD Engineering Innovations

• Industry-First Visualization: Pioneered a breakthrough "metal and diffusion cut viewer" inside Synopsys Custom Compiler to dynamically resolve advanced sub-20nm layout constraints. By overlaying cut-masks directly onto drawn wires in real-time, drastically reduced human error, accelerated layout comprehension, and mitigated severe engineer eye strain.
• Perceptual Layer Optimization: Designed a novel layout layer coloring scheme that coded system layer visuals and stipples to align with human eye color sensitivity, enabling the generation of easily identifiable color interference patterns.
• Process-Agnostic CAD Automation: Engineered an abstract, process-non-specific layer/purpose lookup architecture. This eliminated the need to maintain or refactor legacy code when migrating across foundry nodes, freeing up engineering cycles to focus purely on deploying new technologies.

DevOps, AI & Environment Management

• Infrastructure as Code (IaC): Achieved 100% immutable system state management by engineering an end-to-end Ansible deployment framework. Enforced a locked-down, local DNF package repository to pin hosts to identical Kernel and package versions across Rocky Linux 8.10, RHEL, and Oracle Linux environments.
• Workspace & Workflow Standardization: Customized Google Repo to manage project workspaces, adding symbolic linking to immutable collateral and engineering pre-push git triggers to enforce automated CI/CD testing before code check-in.
• Deterministic Project Environments: Deployed direnv with a proprietary tool-versioning wrapper, reducing vendor file-path complexity by dynamically injecting version-specific EDA environment settings per project.
• AI Tooling Containerization: Maintained bleeding-edge developer velocity by containerizing GitHub Copilot within a specialized Singularity (Apptainer) Ubuntu container, running natively on secure Rocky Linux 8.10 environments.
• Security & Identity Governance: Established a centralized FreeIPA fabric managing enterprise authentication, DNS, and an internal Certificate Authority (CA) to enable seamless SSL/TLS across local web nodes, utilizing HashiCorp Vault and Bitwarden for secure credential management.

Role Overview:
Served as the dual-track DevOps, IT, and CAD Technical Lead with full root access across all enterprise networks. Spearheaded the architecture, qualification, and rollout of core infrastructure, workload management engines, and development workflows. Led multi-team efforts to dismantle legacy monolithic systems, standardize testing, and implement strict design data isolation for secure domestic and contract engineering collaboration.

TECHNICAL ARCHITECTURE & CAD LEADERSHIP ACHIEVEMENTS

Infrastructure & DevOps Architecture

• Enterprise SCM Architecture: Successfully managed the migration of the corporate source control from a Perforce submit/proxy model to a high-availability Commit/Edge model. Wrote a custom Python3 Perforce blackbox test suite measuring high-volume and large-file performance, discovering a critical non-atomic edge-submit bug that was escalated and resolved directly with Perforce.
• Infrastructure Ownership: Stood up and managed the primary engineering stack, including Jenkins CI/CD, Perforce, IPLM/PiCache, Slurm, Nomad, LSF, Apache, FlexLM, and LM-X license daemons.
• Data-Driven Telemetry: Designed and deployed an automated observability suite utilizing ELK Stack, and Prometheus/Grafana to analyze, track, and alert on corporate EDA license utilization trends.
• Secure Workforce Collaboration: Engineered an advanced workspace sharing framework enabling secure cross-collaboration between direct US employees and external contractors. Leveraged Unix organization groups, localized Perforce permissions, and a custom share utility to safely abstract and isolate corporate intellectual property.

Advanced Software & CAD Tool Automation

• Process-Isolated Environment Modules: Architected a comprehensive shift away from rigid "flow-defined shell environments" to a centralized Environment Modules framework. Developed a full-featured Python3 administrator toolkit to recursively test, release, promote, and manage toolchains, allowing concurrent projects on different networks to run seamlessly without code merges.
• Abstract Compute Submitter (Ruby/YAML): Built a process-agnostic, tree-based abstract job submission engine called via API in the main hardware flows. Leveraged hierarchical YAML label configurations to dynamically match memory and compute requirements across varying Slurm/LSF blocks.
• Workload Manager Profiler: Developed a synthetic workload profiler in Python3 and Plotly to benchmark Slurm and LSF performance under max loads. Measured scheduler flap and cgroups guard-railing performance penalties across memory, compute, and subprocess-intensive tasks, delivering data essential for hardware flow optimization.
• DSPF Netlist Pruning API: Integrated Concept Starvision and built a custom structural tracer API to prune massive post-layout netlists. By dynamically dropping or keeping specific netlist objects and arcs, dramatically accelerated simulation times and made previously un-simulatable blocks fully viable.
• IPLM Identity Integration: Driven the adoption of Methodics IPLM for design management. Built the enterprise authentication layer using Python3 and Pamela to hook directly into the centralized FreeIPA infrastructure, automating user group synchronization.
• Standardized Quality Engineering: Introduced standardized test runners across the CAD organization, enabling both sequential and concurrent system testing frameworks to run natively inside or outside of Jenkins pipelines. Managed virtual production runtimes across Python, Ruby/Rake, and Tcl.

Role Overview:
Served as the Technical Lead on core design flows and command-line automation tools optimizing standard cell layout merging and top-level netlisting. Architected massive data-aggregation pipelines for flagship Silicon devices, driving strict code quality standards, concurrent test discovery, and automated deployment architectures across the organization.

Technical Architecture & Software Accomplishments:

• Lynx Flow Integration: Served as the Technical Lead wrapping foundational layout merging and command-line netlisting tools directly into the Synopsys Lynx Design System, engineering an agile platform that supported diverse and complex user models.
• Stratix 10 Parasitic Analytics: Architected and developed a load-on-demand parasitic database engine to manage the extraction of 43 Million D_NETs (with aggressors) for the Stratix 10 device. This breakthrough minimized time/space complexity, isolated SPEF errors, and enabled high-yield timing modeling and optimization.
• Parasitic Quality Assurance (QA) Standard: Pioneered the checks and automated flows required to accurately parse early, dirty, or incomplete SPEF/SPF deliveries. This framework became the corporate Design Standard for early parasitic feedback and timing closure acceleration.
• Quality Engineering & Scaffolding: Designed a multi-language software project scaffold generator that bundled base definitions, modules, automated Doxygen documentation, and custom deployment Makefiles. Built a concurrent regression testing framework executing via Makefile with native unittest/doctest (Python) and tcltest (Tcl) integration.
• Context-Preserving Liberty Parser: Solely engineered a custom Python-based Liberty Parser and API that fully preserved structural context, enabling downstream applications to dynamically create, modify, and merge complex Liberty files.

Role Overview:
Drove 16 years of structural CAD engineering innovation spanning complex algorithmic chip assembly, custom router engines, and layout visualizers. Collaborated closely with tier-one EDA vendors to refine industry-standard design tools, while training global engineering teams on advanced automation.

Front-End Engineering Accomplishments:

• Hierarchical Netlist Tracing & Debugging: Introduced the Concept Engineering StarVision platform to the corporation. Wrote custom Tcl APIs for hierarchical netlist pruning and robust net tracing with configurable arcs, radically reducing runtime simulation overhead and isolating precise test cases.
• Timing Correlation Framework: Developed a multi-threaded, parallel job submission engine in Python that cross-correlated hundreds of concurrent HSPICE and PrimeTime jobs mapped via XLSX matrices, executing across automated LSF clusters.
• Static Connectivity & Chip Assembly: Led the development of an enterprise Static Connectivity Checks platform providing comprehensive textual and graphical debugging. Acted as Technical Lead on the Stratix 5 chip assembly platform utilizing Cadence DFII, SKILL, and IPC.

Back-End Engineering & Algorithmic Accomplishments:

• Modular Design Tiler: Architected a revolutionary hierarchical tiler and chip assembly methodology that became the corporate standard across 5 consecutive technology nodes. Built using Cadence DFII, SKILL, and Perl, the system assembled entire devices relative to placement formulas in minutes, scaling flawlessly across family variants.
• Shape-Based DRD Engine: Solely responsible for the core visualizer and engine of a shape-based, Design Rule Driven (DRD) Layout editing platform. This exact use-model was subsequently adopted by Cadence Design Systems into their commercial tools following a close technical collaboration.
• Global Technical Training: Developed full training modules for DRD Layout and SKILL programming, personally conducting multi-week, on-site engineering boot camps at the Altera Technology Center in Penang, Malaysia.
• Channel Routing Automation: Engineered a standalone optimizer, placer, and auto-router that slashed schematic and routing channel generation time from weeks to seconds. Coded in Perl and SKILL, it dynamically calculated track patterns, shielding requirements, and buffer locations, while automatically dividing long signals.
• Physical Net Extraction API: Programmed a custom physical net extraction tool that became the de facto "mark net" command inside Virtuoso Layout, supporting short handling, block/exit constraints, marker layers, and shortest-path identification.

Role Overview:
Managed block layout and tape-out delivery schedules across flagship projects and foundry nodes, while actively tracking design inefficiencies to build automated software workarounds.

Key Technical Accomplishments:

• First Corporate Intranet Deployment: Stood up Altera’s first-ever internal Apache web server, constructing custom Perl/CGI web interfaces to securely execute local command-line infrastructure tools.
• Automated Bonding Diagram Flow: Architected an intranet-driven Bonding Diagram generation system that checked lead frame repositories and validated layout errors via automated AutoLISP engines running inside AutoCAD. This optimization reduced human error and drove a >10x measurable increase in engineering productivity.
• Tape-Out Operations: Executed strict tape-out duties, generated robust layout test frames, and analyzed EMIB interconnect data.

• Founded an independent technology consulting firm providing full-stack website engineering, graphic design, and marketing consultation.
• Delivered custom client software, data pipelines, and visual branding assets utilizing HTML, JavaScript, Perl/CGI, Adobe Illustrator, and Photoshop.