+ FPGA/pSoC lead: Architecture, RTL design, verification. Methodology, scheduling/planning, mentoring + Xilinx Virtex2, Virtex2Pro, Spartan3, Virtex4 with 3.125GBaud SerDes and on-chip PowerPC405s + Verilog with OVA. ModelSim. Synplicity. EDK Platform Studio + Applications include dataplane fabric & post-processing for telco-grade IPTV delivery/access node platform
Achievements: Architected as a library of parameterized & reusable modules, the Fabric spanned some 20 distinct FPGA designs distributed across a variety of SerDes-connected Switch, Processor and I/O cards. It contained complex controllers and state machines, in select cases even employing multiple on-chip PowerPC 405 subsystems. It reconciled the disparity of TCP/IP packets, ATM cells, TDM channels & MPEG transport streams. It glued, transformed, parsed headers, disassembled/converged/reassembled traffic threads, classified, priority-routed, flow-controlled, de-jittered, buffered in both on and off-chip RAM.
Interfaced to RF (QAM, AMVSB, QPSK), MTS, 6415 DSP (EMIF with DMA), xDSL, T1/E1, T3/E3, OC3/12/48, IMA, 10/100/1000 Ethernet, QDR SRAM, XAUI, SPI3, Intel IXP2800 CSIX, 1250 IXB/NP, APPI, SBI, POSPHY2, UTOPIA2.
Set-up functional simulation framework with clean, layered structure and comprehensive scope, which paid off in the rapid board bring-up and bug-free final product.
As the lead of a team of 3, defined & instituted FPGA development process for design correctness, re-use, manageability & portability. This resulted in significant time-to-market edge.
Through meticulous analysis of the functions to implement, achieved elegant simplicity and complexity without complication… which opened the gates for doing more in less silicon & so helped the bottom line.
> Received formal training in System Verilog
> Received 'Leader of the Pack Award' for leading by example
> Received 'Certificate of Achievement' for succeeding to accommodate a major last-minute feature change